Xilinx Vivado 2015.2 Crack 14
the contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (fpga) practical. starting from experimental observation and analysis of the entropy source in fpga, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. this parametrized design is implemented in a xilinx artix-7 fpga, where the carry chains in the fpga are explored to realize the precise phase shifting. the generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. the prototype integrates 64 circuit units in the fpga to provide a total output throughput of 7.68 gbps, which meets the requirement of current high-speed quantum key distribution systems. the randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.
in this paper, we propose a novel parallel architecture for fast hardware implementation of elliptic curve point multiplication (ecpm), which is the key operation of an elliptic curve cryptography processor. the point multiplication over binary fields is synthesized on both fpga and asic technology by designing fast elliptic curve group operations in jacobian projective coordinates. a novel combined point doubling and point addition (pdpa) architecture is proposed for group operations to achieve high speed and low hardware requirements for ecpm. it has been implemented over the binary field which is recommended by the national institute of standards and technology (nist). the delay of a 233-bit point multiplication is only 3.05 and 3.56 s, in a xilinx virtex-7 fpga, for koblitz and random curves, respectively, and 0.81 s in an asic 65-nm technology, which are the fastest hardware implementation results reported in the literature to date. in addition, a 163-bit point multiplication is also implemented in fpga and asic for fair comparison which takes around 0.33 and 0.46 s, respectively. the area-time product of the proposed point multiplication is very low compared to similar designs. the performance ([formula: see text]) and area time energy (ate) product of the proposed design are far better than the most significant studies found in the literature.
this paper presents a novel design of an adaptive pre-distortion power amplifier (pdpa) with a fully digital pre-distortion algorithm to realize a fast adaptive-circuit power amplifier for radio frequency (rf) signals. the pre-distortion is one of the most effective methods to deal with the distortion problem of traditional analog rf power amplifier, which can cancel the first order intermodulation distortion (imd1). however, its increasing computational complexity for the high order imd (i.e. imd2) makes it difficult to implement in a digital radio frequency integrated circuit (rfic). therefore, adaptive pre-distortion method based on the error model of a power amplifier in the closed-loop is important. in this paper, an on-chip fft approach is used for complex analysis and an analytical model, which can accurately predict the operating behavior of an rf power amplifier in the closed-loop, is proposed. two strategies for adaptive pre-distortion are implemented in this paper, including a fast adaptive pre-distortion and a slow adaptive pre-distortion. the experimental results show that the proposed designs achieve lower imd2 responses than the previous work using the same rfic. in addition, the adaptive pre-distortion based on error model can achieve a similar imd2 response as the automatic gain control, which requires no additional digital hardware.
ieee 802.11ac wave 2 is the first amendment to the ieee 802.11 standard for wireless local area networks (wlans). this wave includes three major improvements to its predecessor ieee 802.11n; increased transmission rate, peak data rate of 6.8 gbps, and new multi-user multiple-input and multiple-output (mu-mimo) capability. to maximize mu-mimo performance, 802.11ac/n/g/b/a/g/f ieee channel bonding is defined to have a maximum channel bonding length of up to 640 meters. however, the high-frequency radio technology, such as complementary code keying (cck) and orthogonal frequency division multiplexing (ofdm), is not suitable for this type of multi-user mimo. in order to improve the channel bonding, the waveform of 802.11ac/n/g/b/a/g/f for the bonding channel must be changed from binary phase-shift keying (bpsk) and quadrature phase-shift keying (qpsk) to a binary offset carrier (boc) format with larger amplitude modulation. in this study, 802.11ac waveform, which is defined in boc, is designed as the bonding channel in the sub-ghz band. the proposed 802.11ac waveform is experimentally evaluated using a 912 mhz ofdm channel bonding system. the experimental results show that the proposed 802.11ac waveform can achieve the optimum channel bonding performance in the sub-ghz band, which shows the suitability of the proposed 802.11ac waveform for the 802.11ac/n/g/b/a/g/f ieee channel bonding.
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